1. Field of the Invention
The present invention relates to a lateral diffused MOSFET (LDMOS) transistor having an elevated gate dielectric structure, which significantly reduces on-resistance (RDSON) while increasing the breakdown voltage and improving the device robustness to hot carrier degradation. The device can be easily integrated with conventional deep sub-micron VLSI processes.
2. Related Art
FIG. 1A is a cross sectional view of a conventional LDMOS transistor 100, which includes P+ substrate 101, P− epitaxial layer 102, deep p-well region 103, P+ backgate contact 104, N+ source region 105, N type reduced surface field region 106, N+ drain contact region 107, gate oxide layer 108, field oxide regions 109-110 and gate electrode 111.
Field oxide regions 109 and 110 are formed simultaneously by conventional local oxidation of silicon (LOCOS) or poly-buffered LOCOS (PBL). Field oxide region 110 provides electrical isolation between LDMOS transistor 100 and other devices (not shown) fabricated in the same substrate. Field oxide region 110 must be relatively thick to provide such isolation. For example, field oxide region 110 typically has a thickness of about 5000 Angstroms or more (depending on the technology node). Because field oxide regions 109 and 110 are thermally grown, half of these oxide regions are grown underneath the silicon surface. Thus, field oxide regions 109 and 110 extend into the silicon surface to a depth of about 2500 Angstroms or more.
Because they are fabricated at the same time, field oxide regions 109 and 110 have the same thickness. Field oxide region 109 is thick enough to protect gate oxide layer 108 from high electric fields that result from voltages applied to drain contact region 107. That is, the field oxide region 109 is sufficiently thick under polysilicon gate electrode 111 where the diffusion region 106 extends between the channel edge and the drain contact region 107. LDMOS transistor 100 is described in more detail in U.S. Pat. No. 6,483,149 to Mosher et al.
In high voltage and power applications, it is desirable to minimize the on-resistance RDSON of LDMOS transistor 100, such that the switch area and power dissipation associated with this transistor 100 is minimized. However, current flowing through LDMOS transistor 100 is forced to bypass the field oxide region 109, thereby resulting in a relatively high on-resistance. That is, the current flowing through LDMOS transistor 100 must flow deep within the silicon, along the relatively long path that exists under field oxide region 109.
FIG. 1B is a cross sectional view of another conventional LDMOS transistor 120, wherein field oxide regions 109 and 110 are replaced by shallow trench isolation (STI) regions 129-130, and polysilicon gate electrode 111 is replaced by polysilicon gate electrode 131. STI regions 129 and 130 are formed simultaneously by conventional methods (i.e., etching trenches in the substrate, and then filling the trenches with dielectric material). STI region 130 provides electrical isolation between LDMOS transistor 120 and other devices (not shown) fabricated in the same substrate. In general, STI region 130 extends deeper below the surface of the substrate in comparison to field oxide region 110, as trench isolation is almost completely below the silicon surface. Thus, in the described example, STI region 130 usually has a depth of about 3500 Angstroms.
Because they are fabricated at the same time, STI regions 129 and 130 have the same depth (e.g., 3500 Angstroms). The large depth of STI region 129 causes LDMOS transistor 120 to exhibit higher on-resistance than LDMOS transistor 100. In addition, the sharp corners typical of STI region 129 (compared to the smooth profile at the LOCOS bird's beak region) locally increases the electric field at those corners, which results in rapid hot carrier degradation and lower breakdown voltage within LDMOS transistor 120.
It would therefore be desirable to have an improved LDMOS transistor that exhibits an on-resistance less than conventional LDMOS transistors. It would further be desirable for such an LDMOS transistor have a compact layout area. It would also be desirable to be able to easily integrate the fabrication of such an LDMOS transistor with conventional deep sub-micron VLSI processes.